Syllabus/Lectures

Lecture 11 Lecture 10 – review add in different arithmetic packages

Week	Date	Topic	Reading Materials
1	8-21-2019	Course Intro	slides
1	8-23-2019	VHDL Intro (guidelines, entity and architecture, basic mux implementation)	slides VHDL Tutorial Mux2x1, testbench
2	8-26-2019	VHDL Intro (if vs. case, priority encoder, structural architectures)	slides mux4x1
	8-28-2019	Arithmetic Operations	slides
	8-30-2019	Lab1	add in different arithmetic packages slides
3	9-2-2019	Holiday
	9-4-2019	Class canceled due to hurricane
	9-6-2019	Carry-Lookahead Adders	slides
4	9-9-2019	Lab 2, Generics, Avoiding Latches	ALU Code Generic Instantiation
	9-11-2019	Sequential Logic	slides reg.vhd reg2.vhd reg2_tb.vhd reg_tb.vhd
	9-13-2019	Lab 3, For-generate	For_If_Generate_Examples
5	9-16-2019	Misc. VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference, Modelsim tricks)	slides
	9-18-2019	Sequential Logic, Cont. Finite State Machines	slides fsm.pdf fsm.vhd
	9-20-2019	Finite State Machines, Cont. Lab 4	codes
6	9-23-2019	Lab 4 Cont., Counters, Integers.	counters
	9-25-2019	FSMD	FIB
	9-27-2019	FSMD, FSM+D, Lab 5	fsmd_examples
7	9-30-2019	Midterm Review	slides
	10-2-2019	Midterm 1
	10-4-2019	Holiday
8	10-7-2019	FSMD, FSM+D, Lab 5, Cont.	fsmd main file is: bit_dff.vhd
	10-9-2019	Midterm 1 Solution, Lab 5	Midterm 1 – Solution
	10-11-2019	Lab 5 Extra Credit, FSMD done protocol, 2-process FSMD
9	10-14-2019	Lab 6 Poor Design Practices	slides
	10-16-2019	ROM, Arrays	slides
	10-18-2019	FPGA Architectures	slides rc_architecture
10	10-21-2019	FPGA Architectures, Cont.
	10-23-2019	FPGA Architectures, Cont.
	10-25-2019	MIPS (Arrays, RAM, Register File) MIPS (Register File, ALU, Datapath)	codes
11	10-28-2019	MIPS (Memory, I/O Ports, Instruction Fetch, Instruction Decode, Register Fetch)
	10-30-2019	Midterm 2 Review	Lecture 13 – review
	11-1-2019	Midterm 2
12	11-4-2019	MIPS (I-type Instructions, Jump Instructions)	Lecture 14
	11-6-2019	MIPS (Branch Instructions, MIF Files, Assembly Code)	Lecture 15
	11-8-2019	MIPS (Branch Instructions, MIF Files, Assembly Code) Metastability, Clock-Domain Crossing	Lecture 15
13	11-11-2019	Holiday
	11-13-2019	Midterm 2 Solution review	Midterm 2 – solution
	11-15-2019	MIPS Performance Buses, Tristates	Lecture 16 Lecture 17
14	11-18-2019	CDC	slides CDC
	11-20-2019	Review 2- Process State Machine – avoid loops
	11-22-2019	Testing of Logic Circuits	lecture 19
15	11-25-2019	Formal Verification of Digital Designs
	11-27-2019	Holiday
	11-29-2019	Holiday
16	12-2-2019	Midterm 3 review	lecture 20 – review
16	12-4-2019	Midterm 3
17

* Special thanks to Prof. Stitt and Gaj for providing their lectures and course materials.

VHDL Resources:

Introductory Video
FPGA Design using VHDL
Dr. Stitt’s Tutorial
VHDL Package Reference
VHDL Math Tricks of The Trade
Tutorial
VHDL Online
VHDL Reference
VHDL Language Reference Guide
Free VHDL Book
Type Conversion Examples
Numerous Verilog Tips (many apply to VHDL)
Tradeoffs between synchronous and asynchronous resets
Excellent article on false paths and multi-cycle paths

Dr. Farimah Farahmandi

Syllabus/Lectures