-- Greg Stitt
-- University of Florida

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg_tb is
end reg_tb;


architecture TB of reg_tb is


  constant TEST_WIDTH : positive := 16;

  signal clk               : std_logic := '0';
  signal rst               : std_logic;
  signal input             : std_logic_vector(TEST_WIDTH-1 downto 0);
  signal output_asynch_rst : std_logic_vector(TEST_WIDTH-1 downto 0);
  signal output_synch_rst  : std_logic_vector(TEST_WIDTH-1 downto 0);

begin  -- TB

  U_ASYNC : entity work.reg(ASYNC_RST)
    generic map (
      width  => TEST_WIDTH)
    port map (
      clk    => clk,
      rst    => rst,
      input  => input,
      output => output_asynch_rst);

  U_SYNC : entity work.reg(SYNC_RST)
    generic map (
      width  => TEST_WIDTH)
    port map (
      clk    => clk,
      rst    => rst,
      input  => input,
      output => output_synch_rst);

  clk <= not clk after 10 ns;

  process
  begin

    rst <= '1';
    input <= (others => '0');
    wait for 100 ns;
    rst <= '0';

    -- test some inputs
    for i in 0 to 2**(TEST_WIDTH-1) loop
      input <= std_logic_vector(to_unsigned(i, TEST_WIDTH));
      wait until clk'event and clk = '1';
    end loop;  -- i

    wait;

  end process;

end TB;