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Publications

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Books

B2. Farimah Farahmandi and Prabhat Mishra, Hardware Trust Validation using Formal Methods, Springer, 2019.
B1. Prabhat Mishra and Farimah Farahmandi, Post-Silicon Validation and Debug, ISBN: 978-3-319-98115-4, Springer, 2018.

Book Chapters

CH7. Farimah Farahmandi and Prabhat Mishra, Post-Silicon SoC Validation Challenges, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH6. Farimah Farahmandi and Prabhat Mishra, Observability-aware Post-Silicon Test Generation, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH5. Farimah Farahmandi and Prabhat Mishra, Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH4. Farimah Farahmandi and Prabhat Mishra, The Future of Post-Silicon Debug, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH3. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, Security and Trust Verification of IoT SoCs, Security and Fault tolerance in Internet of Things,, S. Chakraborty and J. Mathew (editors), Springer, 2018.

CH2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification , The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

CH1. Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

Journal Papers

J5. Adib Nahiyan, Jungmin Park, Miao He,Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation,” Submitted to Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.

J4. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Post-Silicon Functional Coverage Analysis using Design-for-Debug,” submitted to IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), 2018.

J3. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits,” IEEE Transactions on Computers (TC), 2018 (to appear).

J2. Adib Nahiyan, Farimah Farahmandi, Domenic Forte, Prabhat Mishra, and Mark Tehranipoor, “Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018 (to appear).

J1. Farimah Farahmandi and Bijan Alizadeh, “Groebner Basis Based Formal Verification of Large Arithmetic Circuits using Gaussian Elimination and Cone-based Polynomial Extraction,” Microprocessors and Microsystems – Embedded Hardware Design, 39(2), pages 83-96, 2015.

Conference Papers

C12. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, “Scalable Hardware Trojan Detection by Interleaving Concrete Simulation and Symbolic Execution,” IEEE International Test Conference (ITC), Phoenix, AZ, October 28 – November 2, 2018.

C11. Alif Ahmed, Farimah Farahmandi, and Prabhat Mishra, “Directed Test Generation using Concolic Testing on RTL models,” Design Automation and Test in Europe (DATE), pages 1538-1543, Dresden, Germany, March 19-23, 2018.

C10. Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra, “Hardware Trojan Detection using ATPG and Model Checking,” International Conference on VLSI Design (VLSI Design), pages 91-96, Pune, India, January 6 – 10, 2018.

C9. Farimah Farahmandi and Prabhat Mishra, “Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction,” IEEE International Conference on Computer Design (ICCD), pages 193-200, Boston, United States, November 5 – 8, 2017.

C8. Farimah Farahmandi and Prabhat Mishra, “FSM Anomaly Detection using Formal Analysis,” IEEE International Conference on Computer Design (ICCD), pages 313-320, Boston, United States, November 5 – 8, 2017.

C7. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Cost-effective analysis of post-silicon functional coverage events,” Design Automation and Test in Europe (DATE), pages 392-397, Lausanne, Switzerland, March 27 – 31, 2017.

C6. Farimah Farahmandi, Yuanwen Huang, and Prabhat Mishra, “Trojan Localization using Symbolic Algebra,” Asia and South Pacific Design Automation Conference (ASPDAC), pages 591-597, Tokyo, Japan, January 16 – 19, 2017 (Nominated for Best Paper Award).

C5. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Arithmetic Circuits,” Design Automation and Test in Europe (DATE), pages 1351-1356, Dresden, Germany, March 14 – 18, 2016.

C4. Farimah Farahmandi, Sandip Ray, and Prabhat Mishra, “Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation,” Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 – 18, 2016.

C3. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, and Prabhat Mishra, “Pre-silicon Security Verification and Validation: A Formal Perspective,” ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, San Francisco, USA., June 7 – 11, 2015.

C2. Farimah Farahmandi, Bijan Alizadeh, and Zainalabedin Navabi, “Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 338-343, Tampa, USA., July 9 – 11, 2014.

C1. Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee,Farimah Farahmandi, and Zainalabedin Navabi, “A new structure for interconnect offline testing,” East-West Design and Test Symposium (EWDTS), pages 1-5, Rostov-on-Don, Russia, September 27-30, 2013.