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Books

B7. M. Tehranipoor, K. Z. Azar, N. Asadi, F. Rahman, H. M. Kamali, and F. Farahmandi, Hardware Security: A Look into the Future, Springer, 2024.

B6. K. Z. Azar, H. M. Kamali, F. Farahmandi, and M. Tehranipoor, Understanding Logic Locking, ISBN 9783031379888, Springer, 2023.

B5. M. Tehranipoor, N. Anandakumar, and F. Farahmandi, Hardware Security Training, Hands-on!, ISBN: 9783031310331, Springer, June 2023.

B4. Farimah Farahmandi, Sree Rajendran, and Mark Tehranipoor, CAD for Hardware Security, ISBN: 9783031268953, Springer, May 2023.

B3. Mark Tehranipoor, Nidish Vashistha, and Farimah Farahmandi, Hardware Security Primitives, ISBN: 9783031191848, Springer, January 2023.

B2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, System-on-Chip Security Validation and Verification, ISBN: 978-3-030-30596-3, Springer, 2020.
B1. Prabhat Mishra and Farimah Farahmandi, Post-Silicon Validation and Debug, ISBN: 978-3-319-98115-4, Springer, 2018.

Book Chapters

CH9. Muhammad Monir Hossain, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, Firmware Protection, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH8. Rafid Muttaki, Nitin Pundir, Mark Tehranipoor, Farimah Farahmandi, Security Assessment on Obfuscation using High-level Synthesis, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH7. Farimah Farahmandi and Prabhat Mishra, Post-Silicon SoC Validation Challenges, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH6. Farimah Farahmandi and Prabhat Mishra, Observability-aware Post-Silicon Test Generation, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH5. Farimah Farahmandi and Prabhat Mishra, Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH4. Farimah Farahmandi and Prabhat Mishra, The Future of Post-Silicon Debug, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH3. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, Security and Trust Verification of IoT SoCs, Security and Fault tolerance in Internet of Things,, S. Chakraborty and J. Mathew (editors), Springer, 2018.

CH2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification , The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

CH1. Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

Patents

P12. F. Farahmandi, M. Tehranipoor, K. Azar, H. Kamali, T. Zhang,  SiP Security Monitoring via Power Noise Variations, T19032

P11. M. Tehranipoor, F. Farahmandi, F. Rahman, H. Kamali, S. Rahman, G. Yui, Clock Gating System and Method for Protecting Hardware Designs,  T19028

P10. F. Farahmandi, M. Tehranipoor, K. Z. Azar, and R. Mutaki, Fault-To-Time Converter Sensor for Low-Overhead Fault Injection Attack Detection, T19045

P9. M. Tehranipoor, M. S. Rahman, K. Z. Azar, H. M. Kamali, F. Farahmandi, and R. Guo, Building and Redaction of Universal Modules, UF Ref. T19030US00

P8. H. M. Kamali, F. Farahmandi, K. Z. Azar, and T. Zhang, Runtime Security Monitoring of Hardware, M. Tehranipoor, UF Ref. T19032US001

P7. Farimah Farahmandi, Nitin Pundir, Fahim Rahman, Mark Tehranipoor, RTL-PSC-Sim: RTL Simulation-based Power Side-channel Analysis, INV-200381, 2020.

P6. Farimah Farahmandi, Muhammad Monir Hossain, Fahim Rahman, Mark Tehranipoor, Hardware-Assisted Dynamic Instruction Obfuscation for Firmware Protection, INV-200422, 2020

P5. A. Stern, S. Tajik, F. Farahmandi, and M, Tehranipoor, Systems and Methods for Laser Probing For Hardware Trojan Detection, A&B Ref. 049648/534021, UF Ref. T18013US001

P4. Farimah Farahmandi, Muhammad Monir Hossain, Fahim Rahman, Mark Tehranipoor, BODIFT: An Automated Framework for Exploitable Buffer Overflow Detection by Information Flow Tracking, INV-210132, 2020

P3. M. Tehranipoor, F. Farahmandi, and H Wang, “SoFI: Security Property-Driven Vulnerability Assessments of ICs against Fault-Injection Attacks,” INV-200394, 2020.

P2. M. Tehranipoor; D. Forte, F. Farahmandi, A. Nahiyan, F. Rahman, M. S. Rahman, “Protecting Obfuscated Circuits against Attacks that Utilize Test Infrastructures,” 11222098, March 2020.

P1. M. Tehranipoor, A. Stern, A. Nahiyan, F. Farahmandi, and F. Rahman, “Method, Apparatus and Computer Program Product For Providing Confidential Integrated Circuit Design,” 11,704,415.

Editorial Notes

E1. F. Farahmandi, A. Srivastava, D. Di Natale, and M. Tehranipoor, Introduction to the Special issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle, ACM Journal of Emerging Technologies in Computing (JETC), 2023.

Journal Paper

J35. Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “Fuzzing for Automated SoC Security Verification: Challenges and Solution, SI: Silicon Lifecycle Management issue of IEEE Design & Test, 2024.

35. T. Zhang, S. Shi, M. H. Rahman, N. Varshney, A. Kulkarni, F. Farahmandi, and M. Tehranipoor, “INSPECT: Investigating Supply Chain and Cyber-Physical Security of Battery Systems,” ePrint, 2024.

J34. Sree Ranjani Rajendran, Nusrat Farzana Dipu, Shams Tarek, Hadi M Kamali, Farimah Farahmandi, and Mark Tehranipoor, “Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities beneath Software,” Transactions on Information Forensics & Security (TIFS), 2024.

J33. D. Saha, S. Tarek, K. Yahyaei, S. Kumar, J. Zhuo, M. Tehranipoor, and F. Farahmandi, “LLM for SoC Security: A Paradigm Shift” 2023, ePrint, https://eprint.iacr.org/2023/1561.pdf

J32. M. H. Monir, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Fuzzing for Automated SoC Security Verification: Challenges and Solutions,” IEEE Design & Test of Computers (D&T), 2024.

J31. M. M. Rahman, S. Tarek, K. Z. Azar, M. Tehranipoor, and F. Farahmandi, “Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions,” IEEE Design & Test of Computers (D&T), 2023.

J30. P. E. Calzada, M. S. U. I. Sami, K. Zamiri Azar, F. Rahman, F. Farahmandi, M. Tehranipoor, “Heterogeneous Integration Supply Chain Integrity through Blockchain and CHSM” in ACM Advancing Computing as a Science & Profession, 2023.

J29. T. Zhang, M. D. Rahman, H. Mardani Kamali, K. Zamiri Azar, F. Farahmandi, “SiPGuard: Run-time System-in-Package Security Monitoring via Power Noise Variation” in IEEE Transactions on Very Large Scale Integration Systems, 2023.

J28. M. Sami Islam, Hadi Marrdani Kamali, Farimah Farahmandi, Fahim Rahman, Mark Tehranipoor, “Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations,” in IEEE Design & Test, 2023.

J27. R. Kibria, F. Farahmandi, and M. Tehranipoor, “FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2023.3266368.

J26. M. S. Rahman, R. Guo, H. M. Kamali, F. Rahman, F. Farahmandi and M. Tehranipoor, “ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach,” in IEEE Access, vol. 11, pp. 19741-19761, 2023, doi: 10.1109/ACCESS.2023.3244902.

J25. T. Zhang, F. Rahman, M. Tehranipoor, and F. Farahmandi, “FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain with Blockchain Technology,” in IEEE Design and Test, 2022.

J24. M. R. Muttaki, R. Mohammadivojdan, H. M. Kamali, M. Tehranipoor, F. Farahmandi, “HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language,” in Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.

J23. N. Pundir, J. Park, F. Farahmandi, and M. Tehranipoor, “Power Side-Channel Leakage Assessment Framework at Register-Transfer Level,” in IEEE Transactions on VLSI (TVLSI), 2022.

J22. J. Park, N. Anandakumar, D. Saha, D. Mehta, N. Pundir, F. Rahman, F. Farahmandi, and M. Tehranipoor, “PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms,” IACR Cryptology ePrint Archive, May 2022, https://eprint.iacr.org/2022/527.pdf

J21. K. Z. Azar, M. M. Hossain, A. Vafaei, H. Al Sheikh, N. Mondol, F. Rahman, M. Tehranipoor, and F. Farahmandi, “Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions,” IACR Cryptology ePrint Archive, March 2022, https://eprint.iacr.org/2022/394.pdf

J20. H. A. Shaikh, M. B. Monjil, S. Chen, F. Farahmandi, N. Asadi, M. Tehranipoor, and F. Rahman, “Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/258.pdf

J19. H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/260.pdf

J18. N. Vashistha, M. L. Rahman, S. Haque, A. Uddin, S. Islam Sami, A. Mazumder, P/ Calzada, F. Farahmandi, N. Asadi, F. Rahman, and M. Tehranipoor, ToSHI – Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance, IACR Cryptology ePrint Archive, August 2022, https://eprint.iacr.org/2022/984.pdf

J17. N. Anandakumar, M. S. Rahman, M. M. Rahman, R. Kibria, U. Das, F. Farahmandi, F. Rahman, M. Tehranipo7r, “Rethinking watermark: Providing Proof of IP Ownership in Modern SoCs,” IACR Cryptology ePrint Archive, Jan. 2022, https://eprint.iacr.org/2022/092.pdf

J16. N. Vashishta, M M. Hossain, R. Shahriar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “eChain: A Blockchain-enabled Ecosystem for Electronic Device Authenticity Verification,” IEEE Transactions on Consumer Electronics (TCE), 2022.

J15. A. Stern, H. Wang, F. Rahim, F. Farahmandi, and M. Tehranipoor, “ACED-IT: Assuring Confidential Electronic Design against Insider Threat in a Zero Trust Environment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems of Integrated Circuits and Systems (TCAD), 2022.

J14. S. Dey, J. Park, N. Pundir, D. Saha, A. mazumdar, D. Mehta, N. Asadi, F. Rahman, F. Farahmandi, and M. Tehranipoor, Secure Physical Design, IACR Cryptology ePrint Archive, May 2022, https://eprint.iacr.org/2022/891

J13. N. Pundir, S. Aftabjahani, R. Cammarota, M. Tehranipoor, and F. Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2022.

J12. M Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor. “Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks,” ACM Trans. Des. Autom. Electron. Syst (TOADES). 26, 4, Article 29 (March 2021), 27 pages. DOI:https://doi.org/10.1145/3444960.

J11. B. Ahmed, K. Bepary, N. Pundir, M. Borza, O. Raikhman, A. Garg, D. Dunchin, A. Cron, M. Abdel-Moneum, F. Farahmandi, F. Rahman, and M. Tehranipoor, “Quantifiable Assurance: From IPs to Platforms,” 2021, https://eprint.iacr.org/2021/1654.pdf

J10. N. Farzana, F. Farahmandi, and M. Tehranipoor, SoC Security Properties and Rules, IACR Cryptology ePrint Archive, 2022.

J9. F. Rahman, F. Farahmandi, and M. Tehranipoor, “An End-to-End Bitstream Tamper Attack Against Flip-chip Package,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/1542.pdf.

J8. N. Farzana, F. Farahmandi, and M. Tehranipoor, “SoC Security Properties and Rules,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/1014.pdf.

J7. Huanyu Wang, Henian Li, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoFI: Security Property-Driven VulnerabilityAssessments of ICs Against Fault-Injection Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.

J6. Mohammad Tanjid Rahman, Mohammad Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail”, Integration, the VLSI Journal, Vol. 72, 2020.

J5. Adib Nahiyan, Jungmin Park, Miao He,Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation,” ACM Transactions on Design Automation ofElectronic Systems (TODAES), Vol. 25, No. 3, 2020.

J4. Adib Nahiyan, Farimah Farahmandi, Domenic Forte, Prabhat Mishra, and Mark Tehranipoor, “Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38. No. 6, 2019.

J3.  F. Farahmandi and P. Mishra, Automated Test Generation for Debugging Multiple Unknown Bugs in Arithmetic Circuits, in IEEE Transaction on Computers (TC), 2018.

J2. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits,” IEEE Transactions on Computers (TC), 2018 .

J1. Farimah Farahmandi and Bijan Alizadeh, “Groebner Basis Based Formal Verification of Large Arithmetic Circuits using Gaussian Elimination and Cone-based Polynomial Extraction,” Microprocessors and Microsystems – Embedded Hardware Design, 39(2), pages 83-96, 2015.

Conference Papers

C82. G. I. Haidar, K. Z. Azar, H. M. Kamali, M. Tehranipoor, F. Farahmandi, “GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Packages”, ACM/IEEE Design Automation Conference (DAC) , 2024.

C81. D. Saha, K. Yahyaei., S. K. Saha, M. Tehranipoor, and F. Farahmandi, “Empowering hardware security with LLM: The development of a vulnerable hardware database,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024.

C80. A. Ayalasomayajula, N. Farzana, D. Pal and F. Farahmandi, “Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024.

C79. Nurun Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi and Mark Tehranipoor, “Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation,Design, Automation and Test in Europe Conference (DATE), 2024.

C78. Dipayan Saha, Katayoon Yahyaei, Sujan Kumar Saha, Farimah Farahmandi “Embracing Large Language Model for System-on-Chip Security,” GOMACTech Conference, 2024.

C77. N. F. Dipu, M. M. Hossain, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection,” Asian and South Pacific Conference on Design Automation Conference (ASP-DAC), 2024.

C76. S. R. Rajendran, F. Farahmandi, and M. Tehranipoor, “CAD Tools Pathways in Hardware Security,” International Conference on VLSI Design (VLSID), 2024.

C75. M. R. Muttaki, H. M. Kamali, M. Tehranipoor and F. Farahmandi, “PALLET: Protecting Analog Devices using a Last-Level Edit Technique,” IEEE Conference on Physical Assurance and inspection of Electronics (PAINE), September 2023.

C74. S. Rahman, N. Varshney, F. Farahmandi, N. Asadi, and M. Tehranipoor, “LLE: Mitigating IC Piracy and Reverse Engineering by Last Level Edit,” International Symposium for Testing and Failure Analysis (ISTFA), November 2023.

C73. R. Kibria, F. Farahmandi and M. Tehranipoor, “ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction,” International Test Conference (ITC), October 2023.

C72. H. Al-Shaikh, M. Bin Monjil, K. Zamiri Azar, F. Farahmandi, M. Tehranipoor and F. Rahman, “QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), October 2023.

C71. M. M. Rahman, S. Tarek, K. Zamiri Azar and F. Farahmandi, “EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), October 2023.

C70. Z. Ibnat, H. Mardani Kamali, F. Farahmandi, “Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), October 2023.

C69. B. Ahmed, F. Farahmandi, “SoC Security Verification: Challenges and Solutions,” SRC TECHCON, September 2023.

C68. M. Monir, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “EmuFuzzer: Emulation-based Cost Function Guided Fuzzing for SoC Vulnerability Detection,” SRC TECHCON, September 2023.

C67. M. Muttaki, Z. Ibnat, S. Shi, H. Mardani Kamali, F. Farahmandi, “Security of Hardware Generators: Enabling Assurance in High-Level Synthesis,” IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), August 2023.

C66. Zahin Ibnat, M Sazadur Rahman, Mridha Mashahedur Rahman, Hadi Mardani Kamali,
Mark Tehranipoor and Farimah Farahmandi, “ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs,” in IEEE/ACM Design Automation Conference, July 2023.

C65. S. Tarek, S. Rajendran, M. Tehranipoor, and F. Farahmandi,Benchmarking of SoC-level Hardware Vulnerabilities: A Complete Walkthrough,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), June 2023.

C64. Sazadur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, and Farimah Farahmandi, “Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking,” in  ACM Great Lakes Symposium on VLSI, (GLSVLSI), June 2023.

C63. Upoma Das, M Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi, “PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates,” IEEE 28th European Test Symposium, May 2023.

C62. Tao Zhang, Mark Tehranipoor, Farimah Farahmandi, “BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering,” IEEE 28th European Test Symposium, May 2023.

C61. R. Muttaki, S. Saha, H. Mardani Kamali, F. Rahman, M. Tehranipoor, and F. Farahmandi, “RTLock: IP Protection using Scan-Aware Logic Locking at RTL,” in IEEE/ACM Design Automation and Test in Europe (DATE), April 2023. (Nominated for Best Paper Award)
C60. R. Guo, Mohammad S. Rahman, H. Mardani Kamali, F. Rahman, F. Farahmandi, and M. Tehranipoor, “EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction,” in IEEE/ACM Design Automation and Test in Europe (DATE), April 2023.
C59. H. Mardani Kamali, K. Zamiri Azar, F. Farahmandi, and M. Tehranipoor, “Shrinking eFPGA Fabrics for Logic Locking,” in IEEE/ACM Design Automation and Test in Europe (DATE), April 2023. (Nominated for Best Paper Award)
C58. S. Ranjani Rajendran, S. Tarek, B. Myers Hicks, H. Mardani Kamali, F. Farahmandi, and M. Tehranipoor, “HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities,” in IEEE/ACM Design Automation and Test in Europe (DATE), April 2023.
C57. M. M. Hossain, A. Vafaei, K. Zamiri Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing,” in IEEE/ACM Design Automation and Test in Europe (DATE), April 2023. (Nominated for Best Paper Award)

C56. Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Muhammad Monir Hossain, Fahim Rahman, “Quantitative Information Flow Analysis of Hardware Designs using Asset Flow Graphs,” GOMACTech Conference, March 2023.

C55. Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “Robust Verification Architecture for Physical Inspection based Chiplet Authentication,” GOMACTech Conference, March 2023.

C54. Shams Tarek, Hadi Mardani Kamali, Farimah Farahmandi, “An ISA-based Software Snippet Generation for Exploiting Hardware Vulnerabilities,” GOMACTech Conference, March 2023.

C53. Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, “Cost Function Assisted Fuzz and Penetration Testing for SoC Security Verification,” GOMACTech Conference, MArch 2023.

C52. Shang Shi, Nitin Pundir, Hadi Mardani Kamali, Mark Tehranipoor, Farimah Farahmandi, “SecHLS: Enabling Security Awareness in High-Level Synthesis,” ASP-DAC 2023, January 2023.

C51. Hasan Al-Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “SHarPen: SoC Security Verification by Hardware Penetration Test,” ASP-DAC 2023, January 2023.

C50. A. Mazumder Shuvo, N. Pundir, J. Park, F. Farahmandi, and M. Tehranipoor, “LDTFI: Layout-Aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), June 2022.

C49. Upoma Das, Md Rafid Muttaki, Mark M. Tehranipoor, Farimah Farahmandi, “ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features,” International Test Conference (ITC), Anaheim, October 2022.

C48. Rasheed Kibria, M Sazadur Rahman, Farimah Farahmandi, Mark Tehranipoor, “RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications,” International Test Conference (ITC), Anaheim, October 2022.

C47. K. Z. Azar, H. M. Kamali, F. Farahmandi, and M. Tehranipoor, “Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, June 2022.

C46. N. Pundir, H. Li, L. Lin, N. Chang, F. Farahmandi, M. Tehranipoor, “Security Properties Driven Pre-Silicon Laser Fault Injection Assessment“, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, June 2022.

C45 R. Muttaki, T. Zhang, Mark Tehranipoor, and F. Farahmandi, “FTC: A Universal Sensor for Fault Injection Attack Detection,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, June 2022.

C44. M. R. Muttaki, Z. Ibnat, F. Farahmandi, “Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis,” IEEE/ACM Design Automation Conference (DAC), July 2022.

C43. S. Rahman, R. Guo, H. M. Kamali, F. Rahman, F. Farahmandi, M. Abdel-Moneum, and M. Tehranipoor, “O’Clock: Lock the Clock via Clock-gating for SoC IP Protection,” Design Automation Conference (DAC), July 2022.

C42. R. Kibria, N. Farzana Dipu, F. Farahmandi, Mark Tehranipoor, “FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security,” IEEE VLSI Test Symposium (VTS), May 2022.

C41. S. Mohammad, M. Rahman, and F. Farahmandi, “ Required Policies and Properties of the Security Engine of an System on Chip,” IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), 2021.

C40. D. Mehra, N. Mondol, F. Farahmandi, and M. Tehranipoor, “AIME: Watermarking AL Models by Leveraging Errors,” IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2022.

C39. T. Zhang, F. Rahman, M. Tehranipoor, and F. Farahmandi, “FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain with Blockchain Technology,” IEEE Workshop on Silicon Lifecycle Management (SLM), Oct. 2021

C38. H. Wang, H. Li, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Security Property-Driven Fault-Injection Vulnerability Assessment of Modern SoCs,” Intel Security Conference (iSecCon), 2021.

C37. S. U. Sami, F. Rahman, D. Donchin, A. Cron, M. Borza, F. Farahmandi, and M. Tehranipoor, “POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2021.

C36. Arash Vafaei, Nick Hooten, Mark Tehranipoor, and Farimah Farahmandi, “SymbA: Symbolic Execution at C-level for Hardware Trojan Activation,” in International Test Conference (ITC), October 2021.

C35. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor, “LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment,” in International Test Conference (ITC), October 2021.

C34. Bulbul Ahmed, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor, “AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow,” in International Conference on Computer Aided Design (ICCAD), November 2021.

C33. Muhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark Tehranipoor, “HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2021.

C32. Rafid Muttaki, Roshanak Mohammadivojdan, Mark Tehranipoor, and Farimah Farahmandi, “HLock: Locking IPs at the High-Level Language,” in ACM/IEEE Design Automation Conference (DAC), December 2021.

C31. Tao Zhang, Jungmin Park, Mark Tehranipoor, and Farimah Farahmandi, “PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation” in ACM/IEEE Design Automation Conference (DAC), December 2021.

C30. Md Sami Ul Islam, Fahim Rahman, Farimah Farahmandi, Adam Cron, Mike Borza†, Mark Tehranipoor, “End-to-End Secure SoC Life cycle Management ,”ACM/IEEE Design Automation Conference (DAC), December 2021.

C29. Sohrab Aftabjahani, Ryan Kastner, Mark Tehranipoor, Farimah Farahmandi, Jason Oberg, Anders Nordstrom, Nicole Fern, and Alric Althoff. “CAD for Hardware Security – Automation is Key to Adoption of Solutions,” In IEEE VLSI Test Symposium (VTS), April 2021.

C28. Farzana, Nusrat, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor. “SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.” In IEEE VLSI Test Symposium (VTS), April 2021.

C27. Nitin Pundir, Farimah Farahmandi, and Mark Tehranipoor. “Secure High-Level Synthesis: Challenges and Solutions,” In IEEE International Symposium on Quality Electronic Design (ISQED), April 2021.

C26. Hunyu Wang, Henian Li, Farimah Farahmandi, Mark Tehranipoor, “SoFI: A Security Property-Driven VulnerabilityAssessment Framework for ICs AgainstFault-Injection Attacks,” in GOMACTech, March 2021.

C25. Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton, Samuel Pagliarini, “Design Obfuscation versus Test,” 2020 IEEE European Test Symposium (ETS), pp. 1-10, May 2020.

C24. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “SPARTA: Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C23. Jason Vosatka, Andrew Stern, Mohammad Monir Hossain, Fahim Rahman, F. Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Tracking Cloned Elecronic Components using a Consortium-based Blockchain Infrastructure,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C22. Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor,, “SPARTA: A Laser Probing Approach for Trojan Detection,” International Test Conference (ITC), 2020.

C21. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “Trust Assessment for Electronic Components using Laser and Emission-based Microscopy,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C20. Jason Vosatka, Andrew Stern, Mohammad Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Confidence Modeling and Tracking of Recycled Integrated Circuits, Enabled by Blockchain,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C19. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization,” in GOMACTech, March 2020.

C18. Andrew Stern, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor, “Sequential Hardware Trojan Detection using Clock Activity Analysis,” in GOMACTech, March 2020.

C17. Jason Vasatka, Mohammad Monir Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Modeling Risk in Electronics Supply Chains, Enabled by Blockchain,” in GOMACTech, March 2020.

C16. Nitin Pundir, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis in SoCs,” in GOMACTech, March 2020.

C15. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment,” in IEEE VLSI Test Symposium (VTS), San Diego, April 5-8, 2020.

C14. Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “FPGA Bitstream Security: A Day in the Life,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C13. Nusrat Farzana, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoC Security Verification using Property Checking,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C12. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, “Scalable Hardware Trojan Detection by Interleaving Concrete Simulation and Symbolic Execution,” IEEE International Test Conference (ITC), Phoenix, AZ, October 28 – November 2, 2018.

C11. Alif Ahmed, Farimah Farahmandi, and Prabhat Mishra, “Directed Test Generation using Concolic Testing on RTL models,” Design Automation and Test in Europe (DATE), pages 1538-1543, Dresden, Germany, March 19-23, 2018.

C10. Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra, “Hardware Trojan Detection using ATPG and Model Checking,” International Conference on VLSI Design (VLSI Design), pages 91-96, Pune, India, January 6 – 10, 2018.

C9. Farimah Farahmandi and Prabhat Mishra, “Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction,” IEEE International Conference on Computer Design (ICCD), pages 193-200, Boston, United States, November 5 – 8, 2017.

C8. Farimah Farahmandi and Prabhat Mishra, “FSM Anomaly Detection using Formal Analysis,” IEEE International Conference on Computer Design (ICCD), pages 313-320, Boston, United States, November 5 – 8, 2017.

C7. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Cost-effective analysis of post-silicon functional coverage events,” Design Automation and Test in Europe (DATE), pages 392-397, Lausanne, Switzerland, March 27 – 31, 2017.

C6. Farimah Farahmandi, Yuanwen Huang, and Prabhat Mishra, “Trojan Localization using Symbolic Algebra,” Asia and South Pacific Design Automation Conference (ASPDAC), pages 591-597, Tokyo, Japan, January 16 – 19, 2017 (Nominated for Best Paper Award).

C5. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Arithmetic Circuits,” Design Automation and Test in Europe (DATE), pages 1351-1356, Dresden, Germany, March 14 – 18, 2016.

C4. Farimah Farahmandi, Sandip Ray, and Prabhat Mishra, “Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation,” Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 – 18, 2016.

C3. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, and Prabhat Mishra, “Pre-silicon Security Verification and Validation: A Formal Perspective,” ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, San Francisco, USA., June 7 – 11, 2015.

C2. Farimah Farahmandi, Bijan Alizadeh, and Zainalabedin Navabi, “Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 338-343, Tampa, USA., July 9 – 11, 2014.

C1. Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee,Farimah Farahmandi, and Zainalabedin Navabi, “A new structure for interconnect offline testing,” East-West Design and Test Symposium (EWDTS), pages 1-5, Rostov-on-Don, Russia, September 27-30, 2013.