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Publications

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Books

B3. Farimah Farahmandi and Mark Tehranipoor, CAD for Hardware Security, Springer, 2021.

B2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, System-on-Chip Security Validation and Verification, ISBN: 978-3-030-30596-3, Springer, 2020.
B1. Prabhat Mishra and Farimah Farahmandi, Post-Silicon Validation and Debug, ISBN: 978-3-319-98115-4, Springer, 2018.

Book Chapters

CH9. Muhammad Monir Hossain, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, Firmware Protection, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH8. Rafid Muttaki, Nitin Pundir, Mark Tehranipoor, Farimah Farahmandi, Security Assessment on Obfuscation using High-level Synthesis, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH7. Farimah Farahmandi and Prabhat Mishra, Post-Silicon SoC Validation Challenges, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH6. Farimah Farahmandi and Prabhat Mishra, Observability-aware Post-Silicon Test Generation, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH5. Farimah Farahmandi and Prabhat Mishra, Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH4. Farimah Farahmandi and Prabhat Mishra, The Future of Post-Silicon Debug, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH3. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, Security and Trust Verification of IoT SoCs, Security and Fault tolerance in Internet of Things,, S. Chakraborty and J. Mathew (editors), Springer, 2018.

CH2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification , The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

CH1. Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

Journal Papers

J9. Nitin Pundir, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, ” What is All the FaaS About? – Remote Exploitation of FPGA-as-a-ServicePlatforms,” Submitted to Springer Journal of Hardware and Systems Security (HASS), 2020.

J8. Nitin Pundir, Mark Tehranipoor, and Farimah Farahmandi, “Analyzing Security Vulnerabilities Induced byHigh-level Synthesis,” Submitted to IEEE Transactions on Computers (TC), 2020.

J7. Huanyu Wang, Henian Li, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoFI: Security Property-Driven VulnerabilityAssessments of ICs Against Fault-Injection Attacks,” Submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.

J6. Mohammad Tanjid Rahman, Mohammad Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail”, Integration, the VLSI Journal, Vol. 72, 2020.

J5. Adib Nahiyan, Jungmin Park, Miao He,Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation,” ACM Transactions on Design Automation ofElectronic Systems (TODAES), Vol. 25, No. 3, 2020.

J4. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Post-Silicon Functional Coverage Analysis using Design-for-Debug,” submitted to IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), 2018.

J3. Adib Nahiyan, Farimah Farahmandi, Domenic Forte, Prabhat Mishra, and Mark Tehranipoor, “Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38. No. 6, 2019.

J2. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits,” IEEE Transactions on Computers (TC), 2018 .

J1. Farimah Farahmandi and Bijan Alizadeh, “Groebner Basis Based Formal Verification of Large Arithmetic Circuits using Gaussian Elimination and Cone-based Polynomial Extraction,” Microprocessors and Microsystems – Embedded Hardware Design, 39(2), pages 83-96, 2015.

Conference Papers

C25. Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton, Samuel Pagliarini, “Design Obfuscation versus Test,” 2020 IEEE European Test Symposium (ETS), pp. 1-10, May 2020.

C24. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “SPARTA: Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C23. Jason Vosatka, Andrew Stern, Mohammad Monir Hossain, Fahim Rahman, F. Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Tracking Cloned Elecronic Components using a Consortium-based Blockchain Infrastructure,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C22. Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor,, “SPARTA: A Laser Probing Approach for Trojan Detection,” International Test Conference (ITC), 2020.

C21. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “Trust Assessment for Electronic Components using Laser and Emission-based Microscopy,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C20. Jason Vosatka, Andrew Stern, Mohammad Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Confidence Modeling and Tracking of Recycled Integrated Circuits, Enabled by Blockchain,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C19. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization,” in GOMACTech, March 2020.

C18. Andrew Stern, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor, “Sequential Hardware Trojan Detection using Clock Activity Analysis,” in GOMACTech, March 2020.

C17. Jason Vasatka, Mohammad Monir Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Modeling Risk in Electronics Supply Chains, Enabled by Blockchain,” in GOMACTech, March 2020.

C16. Nitin Pundir, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis in SoCs,” in GOMACTech, March 2020.

C15. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment,” in IEEE VLSI Test Symposium (VTS), San Diego, April 5-8, 2020.

C14. Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “FPGA Bitstream Security: A Day in the Life,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C13. Nusrat Farzana, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoC Security Verification using Property Checking,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C12. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, “Scalable Hardware Trojan Detection by Interleaving Concrete Simulation and Symbolic Execution,” IEEE International Test Conference (ITC), Phoenix, AZ, October 28 – November 2, 2018.

C11. Alif Ahmed, Farimah Farahmandi, and Prabhat Mishra, “Directed Test Generation using Concolic Testing on RTL models,” Design Automation and Test in Europe (DATE), pages 1538-1543, Dresden, Germany, March 19-23, 2018.

C10. Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra, “Hardware Trojan Detection using ATPG and Model Checking,” International Conference on VLSI Design (VLSI Design), pages 91-96, Pune, India, January 6 – 10, 2018.

C9. Farimah Farahmandi and Prabhat Mishra, “Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction,” IEEE International Conference on Computer Design (ICCD), pages 193-200, Boston, United States, November 5 – 8, 2017.

C8. Farimah Farahmandi and Prabhat Mishra, “FSM Anomaly Detection using Formal Analysis,” IEEE International Conference on Computer Design (ICCD), pages 313-320, Boston, United States, November 5 – 8, 2017.

C7. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Cost-effective analysis of post-silicon functional coverage events,” Design Automation and Test in Europe (DATE), pages 392-397, Lausanne, Switzerland, March 27 – 31, 2017.

C6. Farimah Farahmandi, Yuanwen Huang, and Prabhat Mishra, “Trojan Localization using Symbolic Algebra,” Asia and South Pacific Design Automation Conference (ASPDAC), pages 591-597, Tokyo, Japan, January 16 – 19, 2017 (Nominated for Best Paper Award).

C5. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Arithmetic Circuits,” Design Automation and Test in Europe (DATE), pages 1351-1356, Dresden, Germany, March 14 – 18, 2016.

C4. Farimah Farahmandi, Sandip Ray, and Prabhat Mishra, “Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation,” Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 – 18, 2016.

C3. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, and Prabhat Mishra, “Pre-silicon Security Verification and Validation: A Formal Perspective,” ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, San Francisco, USA., June 7 – 11, 2015.

C2. Farimah Farahmandi, Bijan Alizadeh, and Zainalabedin Navabi, “Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 338-343, Tampa, USA., July 9 – 11, 2014.

C1. Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee,Farimah Farahmandi, and Zainalabedin Navabi, “A new structure for interconnect offline testing,” East-West Design and Test Symposium (EWDTS), pages 1-5, Rostov-on-Don, Russia, September 27-30, 2013.

Patents

P2. Mark Tehranipoor, Domenic Forte, Farimah Farahmandi, Adib Nahiyan, Fahim Rahman, Mohammad Sazadur Rahman, “Protecting Obfuscated Circuits Against Attacks That Utilize Test Infrastructures,” August 2019.

P1. Mark Tehranipoor, Andrew Stern, Adib Nahiyan, Farimah Farahmandi, and Fahim Rahman, “Method, Apparatusand Computer Program Product For Providing Confidential Integrated Circuit Design,” August 2019.