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Books

B4. Mark Tehranipoor, Nidish Vashistha, and Farimah Farahmandi, Hardware Security Premitives, January 2022.

B3. Farimah Farahmandi, Sree Rajendran, and Mark Tehranipoor, CAD for Hardware Security, Springer, 2021.

B2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, System-on-Chip Security Validation and Verification, ISBN: 978-3-030-30596-3, Springer, 2020.
B1. Prabhat Mishra and Farimah Farahmandi, Post-Silicon Validation and Debug, ISBN: 978-3-319-98115-4, Springer, 2018.

Book Chapters

CH9. Muhammad Monir Hossain, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, Firmware Protection, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH8. Rafid Muttaki, Nitin Pundir, Mark Tehranipoor, Farimah Farahmandi, Security Assessment on Obfuscation using High-level Synthesis, Emerging Topics in Hardware Security, Mark Tehranipoor (Editor), Springer, 2020.

CH7. Farimah Farahmandi and Prabhat Mishra, Post-Silicon SoC Validation Challenges, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH6. Farimah Farahmandi and Prabhat Mishra, Observability-aware Post-Silicon Test Generation, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH5. Farimah Farahmandi and Prabhat Mishra, Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH4. Farimah Farahmandi and Prabhat Mishra, The Future of Post-Silicon Debug, Post-Silicon Validation and Debug, P. Mishra, F. Farahmandi (editors), Springer, 2018.

CH3. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, Security and Trust Verification of IoT SoCs, Security and Fault tolerance in Internet of Things,, S. Chakraborty and J. Mathew (editors), Springer, 2018.

CH2. Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification , The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

CH1. Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.

Patents

P3. M. Tehranipoor, F. Farahmandi, and H Wang, “Security Property-Driven Vulnerability Assessments of ICs against Fault-Injection Attacks,” June 2022.
P2. M. Tehranipoor; D. Forte, F. Farahmandi, A. Nahiyan, F. Rahman, M. S. Rahman, “Protecting Obfuscated Circuits against Attacks that Utilize Test Infrastructures,” March 2020.
P1. M. Tehranipoor, A. Stern, A. Nahiyan, F. Farahmandi, and F. Rahman, “Method, Apparatus and Computer Program Product For Providing Confidential Integrated Circuit Design,” August 2019.

Journal Paper

J19. N. Pundir, J. Park, F. farahmandi, and M. Tehranipoor, “Power Side-Channel Leakage Assessment Framework at Register-Transfer Level,” IEEE Transactions on VLSI (TVLSI), 2022.

J18. J. Park, N. Anandakumar, D. Saha, D. Mehta, N. Pundir, F. Rahman, F. Farahmandi, and M. Tehranipoor, “PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms,” IACR Cryptology ePrint Archive, May 2022, https://eprint.iacr.org/2022/527.pdf

J17. K. Z. Azar, M. M. Hossain, A. Vafaei, H. Al Sheikh, N. Mondol, F. Rahman, M. Tehranipoor, and F. Farahmandi, “Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions,” IACR Cryptology ePrint Archive, March 2022, https://eprint.iacr.org/2022/394.pdf

J16. H. A. Shaikh, M. B. Monjil, S. Chen, F. Farahmandi, N. Asadi, M. Tehranipoor, and F. Rahman, “Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/258.pdf

J15. H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/260.pdf

J14. N. N. Anandakumar, M. S. Rahman, M. M. M. Rahman, R. Kibria, U. Das, F. Farahmandi, F. Rahman, M. Tehranipoor, “Rethinking watermark: Providing Proof of IP Ownership in Modern SoCs,” IACR Cryptology ePrint Archive, Jan. 2022, https://eprint.iacr.org/2022/092.pdf

J13. N. Vashishta, M M. Hossain, R. Shahriar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “eChain: A Blockchain-enabled Ecosystem for Electronic Device Authenticity Verification,” IEEE Transactions on Consumer Electronics (TCE), 2022.

J12. A. Stern, H. Wang, F. Rahim, F. Farahmandi, and M. Tehranipoor, “ACED-IT: Assuring Confidential Electronic Design against Insider Threat in a Zero Trust Environment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems of Integrated Circuits and Systems (TCAD), 2022.

J11. N. Pundir, S. Aftabjahani, R. Cammarota, M. Tehranipoor, and F. Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2022.

J10. M Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor. “Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks,” ACM Trans. Des. Autom. Electron. Syst (TOADES). 26, 4, Article 29 (March 2021), 27 pages. DOI:https://doi.org/10.1145/3444960.

J9. B. Ahmed, K. Bepary, N. Pundir, M. Borza, O. Raikhman, A. Garg, D. Dunchin, A. Cron, M. Abdel-Moneum, F. Farahmandi, F. Rahman, and M. Tehranipoor, “Quantifiable Assurance: From IPs to Platforms,” 2021, https://eprint.iacr.org/2021/1654.pdf

J8. F. Rahman, F. Farahmandi, and M. Tehranipoor, “An End-to-End Bitstream Tamper Attack Against Flip-chip Package,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/1542.pdf.

J7. Huanyu Wang, Henian Li, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoFI: Security Property-Driven VulnerabilityAssessments of ICs Against Fault-Injection Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.

J6. Mohammad Tanjid Rahman, Mohammad Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail”, Integration, the VLSI Journal, Vol. 72, 2020.

J5. Adib Nahiyan, Jungmin Park, Miao He,Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation,” ACM Transactions on Design Automation ofElectronic Systems (TODAES), Vol. 25, No. 3, 2020.

J4. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Post-Silicon Functional Coverage Analysis using Design-for-Debug,” submitted to IEEE Transactions On Very Large Scale Integration (VLSI) Systems (TVLSI), 2018.

J3. Adib Nahiyan, Farimah Farahmandi, Domenic Forte, Prabhat Mishra, and Mark Tehranipoor, “Security-aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38. No. 6, 2019.

J2. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits,” IEEE Transactions on Computers (TC), 2018 .

J1. Farimah Farahmandi and Bijan Alizadeh, “Groebner Basis Based Formal Verification of Large Arithmetic Circuits using Gaussian Elimination and Cone-based Polynomial Extraction,” Microprocessors and Microsystems – Embedded Hardware Design, 39(2), pages 83-96, 2015.

Conference Papers

C50. A. Mazumder Shuvo, N. Pundir, J. Park, F. Farahmandi, and M. Tehranipoor, “LDTFI: Layout-Aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022.

C49. Upoma Das, Md Rafid Muttaki, Mark M. Tehranipoor, Farimah Farahmandi, “ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features,” International Test Conference (ITC), Anaheim, 2022.

C48. Rasheed Kibria, M Sazadur Rahman, Farimah Farahmandi, Mark Tehranipoor, “RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications,” International Test Conference (ITC), Anaheim, 2022.

C47. K. Z. Azar, H. M. Kamali, F. Farahmandi, and M. Tehranipoor, “Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, 2022.

C46. N. Pundir, H. Li, L. Lin, N. Chang, F. Farahmandi, M. Tehranipoor, “Security Properties Driven Pre-Silicon Laser Fault Injection Assessment“, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, 2022.

C45 R. Muttaki, T. Zhang, Mark Tehranipoor, and F. Farahmandi, “FTC: A Universal Sensor for Fault Injection Attack Detection,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) WIP, 2022.

C44. M. R. Muttaki, Z. Ibnat, F. Farahmandi, “Secure by Construction: Addressing SecurityVulnerabilities Introduced During High-level Synthesis,” IEEE/ACM Design Automation Conference (DAC), 2022.

C43. S. Rahman, R. Guo, H. M. Kamali, F. Rahman, F. Farahmandi, M. Abdel-Moneum, and M. Tehranipoor, “O’Clock: Lock the Clock via Clock-gating for SoC IP Protection,” Design Automation Conference (DAC), 2022.

C42. R. Kibria, N. Farzana Dipu, F. Farahmandi, Mark Tehranipoor, “FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security,” IEEE VLSI Test Symposium (VTS), 2022.

C41. S. Mohammad, M. Rahman, and F. Farahmandi, “ Required Policies and Properties of the Security Engine of an System on Chip,” IEEE International Symposium on Smart Electronic Systems (IEEE-iSES), 2021.

C40. D. Mehra, N. Mondol, F. Farahmandi, and M. Tehranipoor, “AIME: Watermarking AL Models by Leveraging Errors,” IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022

C39. T. Zhang, F. Rahman, M. Tehranipoor, and F. Farahmandi, “FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain with Blockchain Technology,” IEEE Workshop on Silicon Lifecycle Management (SLM), Oct. 2021

C38. H. Wang, H. Li, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Security Property-Driven Fault-Injection Vulnerability Assessment of Modern SoCs,” Intel Security Conference (iSecCon), 2021.

C37. S. U. Sami, F. Rahman, D. Donchin, A. Cron, M. Borza, F. Farahmandi, and M. Tehranipoor, “POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2021.

C36. Arash Vafaei, Nick Hooten, Mark Tehranipoor, and Farimah Farahmandi, “SymbA: Symbolic Execution at C-level for Hardware Trojan Activation,” in International Test Conference (ITC), October 2021.

C35. Sazadur Rahman, Henian Li, Rui Guo, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor, “LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment,” in International Test Conference (ITC), October 2021.

C34. Bulbul Ahmed, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor, “AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow,” in International Conference on Computer Aided Design (ICCAD), November 2021.

C33. Muhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark Tehranipoor, “HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2021.

C32. Rafid Muttaki, Roshanak Mohammadivojdan, Mark Tehranipoor, and Farimah Farahmandi, “HLock: Locking IPs at the High-Level Language,” in ACM/IEEE Design Automation Conference (DAC), December 2021.

C31. Tao Zhang, Jungmin Park, Mark Tehranipoor, and Farimah Farahmandi, “PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation” in ACM/IEEE Design Automation Conference (DAC), December 2021.

C30. Md Sami Ul Islam, Fahim Rahman, Farimah Farahmandi, Adam Cron, Mike Borza†, Mark Tehranipoor, “End-to-End Secure SoC Life cycle Management ,”ACM/IEEE Design Automation Conference (DAC), December 2021.

C29. Sohrab Aftabjahani, Ryan Kastner, Mark Tehranipoor, Farimah Farahmandi, Jason Oberg, Anders Nordstrom, Nicole Fern, and Alric Althoff. “CAD for Hardware Security – Automation is Key to Adoption of Solutions,” In IEEE VLSI Test Symposium (VTS), April 2021.

C28. Farzana, Nusrat, Avinash Ayalasomayajula, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor. “SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.” In IEEE VLSI Test Symposium (VTS), April 2021.

C27. Nitin Pundir, Farimah Farahmandi, and Mark Tehranipoor. “Secure High-Level Synthesis: Challenges and Solutions,” In IEEE International Symposium on Quality Electronic Design (ISQED), April 2021.

C26. Hunyu Wang, Henian Li, Farimah Farahmandi, Mark Tehranipoor, “SoFI: A Security Property-Driven VulnerabilityAssessment Framework for ICs AgainstFault-Injection Attacks,” in GOMACTech, March 2021.

C25. Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton, Samuel Pagliarini, “Design Obfuscation versus Test,” 2020 IEEE European Test Symposium (ETS), pp. 1-10, May 2020.

C24. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “SPARTA: Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C23. Jason Vosatka, Andrew Stern, Mohammad Monir Hossain, Fahim Rahman, F. Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Tracking Cloned Elecronic Components using a Consortium-based Blockchain Infrastructure,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.

C22. Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor,, “SPARTA: A Laser Probing Approach for Trojan Detection,” International Test Conference (ITC), 2020.

C21. Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujwall Guin, Farimah Farahmandi, and Mark Tehranipoor, “Trust Assessment for Electronic Components using Laser and Emission-based Microscopy,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C20. Jason Vosatka, Andrew Stern, Mohammad Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Confidence Modeling and Tracking of Recycled Integrated Circuits, Enabled by Blockchain,” IEEE Research and Applications of Photonics in Defense Conference (RAPID), August, 2020.

C19. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization,” in GOMACTech, March 2020.

C18. Andrew Stern, Shahin Tajik, Farimah Farahmandi, and Mark Tehranipoor, “Sequential Hardware Trojan Detection using Clock Activity Analysis,” in GOMACTech, March 2020.

C17. Jason Vasatka, Mohammad Monir Hossain, Fahim Rahman, Jeffery Allen, Monica Allen, Farimah Farahmandi, and Mark Tehranipoor, “Modeling Risk in Electronics Supply Chains, Enabled by Blockchain,” in GOMACTech, March 2020.

C16. Nitin Pundir, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis in SoCs,” in GOMACTech, March 2020.

C15. Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment,” in IEEE VLSI Test Symposium (VTS), San Diego, April 5-8, 2020.

C14. Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor, “FPGA Bitstream Security: A Day in the Life,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C13. Nusrat Farzana, Fahim Rahman, Mark Tehranipoor, and Farimah Farahmandi, “SoC Security Verification using Property Checking,” in IEEE International Test Conference (ITC), Washington, DC, November 11-14, 2019.

C12. Alif Ahmed, Farimah Farahmandi, Yousef Iskander, and Prabhat Mishra, “Scalable Hardware Trojan Detection by Interleaving Concrete Simulation and Symbolic Execution,” IEEE International Test Conference (ITC), Phoenix, AZ, October 28 – November 2, 2018.

C11. Alif Ahmed, Farimah Farahmandi, and Prabhat Mishra, “Directed Test Generation using Concolic Testing on RTL models,” Design Automation and Test in Europe (DATE), pages 1538-1543, Dresden, Germany, March 19-23, 2018.

C10. Jonathan Cruz, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra, “Hardware Trojan Detection using ATPG and Model Checking,” International Conference on VLSI Design (VLSI Design), pages 91-96, Pune, India, January 6 – 10, 2018.

C9. Farimah Farahmandi and Prabhat Mishra, “Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction,” IEEE International Conference on Computer Design (ICCD), pages 193-200, Boston, United States, November 5 – 8, 2017.

C8. Farimah Farahmandi and Prabhat Mishra, “FSM Anomaly Detection using Formal Analysis,” IEEE International Conference on Computer Design (ICCD), pages 313-320, Boston, United States, November 5 – 8, 2017.

C7. Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra, “Cost-effective analysis of post-silicon functional coverage events,” Design Automation and Test in Europe (DATE), pages 392-397, Lausanne, Switzerland, March 27 – 31, 2017.

C6. Farimah Farahmandi, Yuanwen Huang, and Prabhat Mishra, “Trojan Localization using Symbolic Algebra,” Asia and South Pacific Design Automation Conference (ASPDAC), pages 591-597, Tokyo, Japan, January 16 – 19, 2017 (Nominated for Best Paper Award).

C5. Farimah Farahmandi and Prabhat Mishra, “Automated Test Generation for Debugging Arithmetic Circuits,” Design Automation and Test in Europe (DATE), pages 1351-1356, Dresden, Germany, March 14 – 18, 2016.

C4. Farimah Farahmandi, Sandip Ray, and Prabhat Mishra, “Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation,” Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 – 18, 2016.

C3. Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, and Prabhat Mishra, “Pre-silicon Security Verification and Validation: A Formal Perspective,” ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, San Francisco, USA., June 7 – 11, 2015.

C2. Farimah Farahmandi, Bijan Alizadeh, and Zainalabedin Navabi, “Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 338-343, Tampa, USA., July 9 – 11, 2014.

C1. Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee,Farimah Farahmandi, and Zainalabedin Navabi, “A new structure for interconnect offline testing,” East-West Design and Test Symposium (EWDTS), pages 1-5, Rostov-on-Don, Russia, September 27-30, 2013.