*LAB WORKAROUNDS
- If you run into unexplainable errors, make sure your Quartus and/or Modelsim projects are stored in a path without any spaces.
- If you are doing a timing simulation, make sure to remove the original vhd file from the Modelsim project. If you don’t, two files will define the same entity, which will likely cause problems.
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If you can’t see the USB-Blaster device in the Quartus Programmer and have your DAD/NAD board plugged in or Waveforms open, try unplugging it or closing Waveforms, and reload the Programmer. This problem occurs since NAD/DAD are FPGA based, Waveforms use JTAG to reprogram different configs, which prevents the Quartus Programmer from using JTAG.
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If you can’t find the USB-Blaster device in Windows, try the following suggestion from another student from previews semesters:
” within device manager, if you double click on the Altera USB-Blaster, and go to the Driver tab, press on Update Driver, then press Browse my computer for driver software -> browse. This is where you find the file. In my case, and for most people, it should be under: Local Disk (C:) -> intelFPGA_lite -> 17.1 -> quartus -> drivers -> usb-blaster. Select that folder and press ok. Then press next in the update driver window and it will load it with functional drivers. “
Lab 0: (One week)
Date: 8/27-2019 – 9/2/2019
- Obtain and test board in lab. If you have questions about the board, you can read the manual here.
- Install Quartus Prime 17.1 Lite Edition (free) . Before downloading, make sure the ModelSim option is selected. You can unselect device support for everything except the MAX 10, MAX II, and MAX V FPGAs if you need to save disk space.
- Tutorial video can be found here. Thanks, John Kearney, for creating it!
- Tutorial video can be found here. Thanks, John Kearney, for creating it!
- Read over the following tutorials (ignore references to lab assignment tasks. You will be using these tools as part of the next lab)
- Review Quartus Tutorials 1 and 3 (Appendices in textbook)
- Start reading the ModelSim tutorial. You do not need to finish the entire tutorial, but you will be using this tool all semester, so make sure you understand the basics. You can install a free version of Modelsim from the earlier Quartus link.
Lab 1: (One week)
Date: 9/5/2019 – 9/11/2019
Lab Instruction
Lab Tutorial
VHDL Codes
Pin Assignment Instructions
Pin Assignment Tutorial
Lab 2: (One week)
Date: 9/12/2019 – 9/18/2019
Primary TA: Carlos
Thanks to Arvind for creating the following ModelSim Tutorial!
Short Testbench (save it as .vhd)
top_level (save it as .vhd)
Useful Links:
VHDL Math Tricks (Comparison of std_logic_arith and numeric_std)
Lab 3: (One week)
Date: 9/19/2019 – 9/25/2019
Primary TA: Muhtadi (Zaki)
Adder Skeleton
Adder Testbench
Top Level Entity
Top_Level for Timing Simulation
Testbench for timing Simulation
Lab 4: (One week)
Date: 9/26/2019 – 10/2/2019
Lab 5: (One week)
Date: 10/14/2019 – 10/18/2019
Primary TA: Carlos Matos
Lab 6: (Two weeks + One week Bonus)
Date: 10/21/2019 – 11/8/2019
Primary TA: Jonathan Cruz
Final Project: (Three weeks)
Date: 11/12/2019 – 12/6/2019